To address a need for faster circuits, a group of integrated circuits can be combined on a common bus and be controlled by a common controller. In such a configuration, each integrated circuit operates in a coordinated manner with other integrated circuits to share data which is transmitted at a high speed. For example, a group of memory devices, such as DRAMs, EEPROMs, or read only memories (ROM), can be connected to a common data bus and be controlled by a memory controller to form a memory system. However, a data rate of the bus may be substantially faster than the maximum operating speed of the individual memories thereby requiring that the data be delayed. Each memory device, therefore, is operated so that while one memory is processing received data, another memory is receiving new data. Such a memory system, with an appropriate number of memory devices and an efficient memory controller, can achieve extremely high speed data transmissions, but an optimal speed can be achieved only if each integrated circuit on the bus can be delayed, as needed, to account for variances within each integrated circuit.
As a transmission rate of the data communication signals in such memory systems continues to increase, new circuitry and methods are needed to accurately clock command data, write data, and read data transmitted between the memory controller and the memory devices. A portion of a clock cycle which can be devoted to clocking valid data becomes quite small, and errors in clocking data can occur at increased transmission speeds because of known effects such as duty cycle variation, bus position of a given memory device, timing drift, loading variations, etc. Therefore, it is desirable to provide small data and/or clock delays to reduce or eliminate deleterious effects of the variations of duty cycle, bus position and so on as stated above.
Further, internal circuit paths are greatly affected by integrated circuit processing parameters, circuit operating temperature, and an operating supply voltage of the circuit. For example, an integrated circuit executes more slowly as operating temperature increases. Integrated circuits also operate more slowly as the operating supply voltage decreases. In either or both of these cases, the duration of the first and second clock signal phases must be extended to provide first and second execution times which are sufficient to accommodate increased first and second minimum execution time periods.
In all of the aforementioned cases, a fine-resolution time delay could alleviate or minimize the problems described. A proper time delay can eliminate or minimize bottle-necks and choke-points in a circuit and can thereby improve an overall circuit throughput when each part of a circuit is operating at its optimum speed. Prior art attempts to provide extremely fine-resolution time delays have been unsuccessful. For example, U.S. Pat. Nos. 6,115,318 and 6,016,282 to Keeth, U.S. Pat. No. 5,812,832 to Horne et al., U.S. Pat. No. 5,644,261 to Frisch et al., and U.S. Patent Application Publication No. 2001/0017558 to Hanzawa et al. each teach a vernier circuit that allows a signal to be shifted in small steps and incorporate a second vernier branch circuit in parallel with a first vernier circuit. These circuits depend on a propagation delay through a time delay element, such as a buffer, to provide for time delays. However, none of these referenced circuits describe or suggest a way to provide for a time shift that is less than a propagation delay of any of the time delay elements. Prior art sampling systems are unable to compensate for fine-resolution variations in sample timing or to select an optimal delay time. Nor do any of the prior art systems provide a method for integrated circuits to compensate for throughput due to variations such as reduced supply voltage or increased operating temperatures.
Therefore, what is needed is an electronic circuit to provide fine-resolution time delays in incremental steps and a method to determine which of those incremental steps is optimal for a given circuit.